Power metal-oxide-semiconductor (MOS) devices, including lateral DMOS devices and vertical DMOS devices, are employed in a variety of applications, such as, for example, power amplifiers in wireless communications systems. Conventional lateral DMOS devices typically exhibit undesirable hot carrier induced (HCI) degradation due at least in part to ionized carriers that become trapped at an upper surface interface between the silicon and oxide of the device. Additionally, lateral DMOS devices generally exhibit relatively low breakdown voltages, compared to vertical DMOS devices, due at least in part to a higher electric field concentration at or near the upper surface of the device. Vertical DMOS devices, on the other hand, typically exhibit reduced gain, due at least in part to a relatively high resistance source contact, and increased reverse transfer capacitance (Crss), which can significantly affect high-frequency (e.g., above 1 gigahertz (GHz)) performance of the device. Consequently, the electrical performance of a vertical DMOS is generally unacceptable, particularly for high-frequency applications.
In many applications, such as, for example, power applications and applications in which high-frequency operation is desired, it is advantageous to minimize the on-resistance associated with the MOS device. In a lateral DMOS device, reduced on-resistance is typically achieved by increasing a doping concentration in a lightly doped drain (LDD) region of the device. However, since the LDD region is typically formed proximate the silicon/oxide interface of the device, increasing the doping concentration of the LDD region also undesirably increases HCI degradation in the device, thereby significantly impacting device reliability.
There exists a need, therefore, for an MOS device capable of improved performance and reliability that does not suffer from one or more of the above-noted deficiencies typically affecting conventional MOS devices. Furthermore, it would be desirable if such an MOS device was fully compatible with standard CMOS process technology.